This invention relates generally to non-volatile semiconductor memory arrays, and more specifically, to non-volatile memory using flash transistors in which over-erase protection is provided.
Non-volatile memory storage systems have progressed rapidly from read-only-memory (ROM) to electrically erasable programmable read-only-memory (EEPROM) Memory arrays using EEPROM cells are desirable because they are easily programmable, can be readily erased, and can store data for an almost indefinite time.
One example of a memory storage system having memory cells with EEPROM elements is described in U.S. Pat. No. 4,725,983, issued to Terada. This system requires a memory cell having two MOS transistors and an FLOTOX type memory transistor. The drawback with this arrangement is that each memory cell requires three transistors which require a large area of silicon, significantly reducing memory density.
Another example of a memory system having memory cells employing EEPROMs is found in U.S. Pat. No. 4,942,556, issued to Sasaki et al. The memory cell therein includes both a MIS transistor and an EEPROM element. Alternatively, the memory cell can employ an EPROM element and a second transistor. The drawback with either cell arrangement is the large area required for the cell structure as compared to a single transistor cell.
Another example of a memory system is U.S. Pat. No. 4,064,494, issued to Dickson et al. This system uses a memory cell which incorporates two non-volatile storage devices. The use of two storage devices again requires more surface area than a single transistor memory cell.
U.S. Pat. No. 4,387,447, issued to Klaas et al., shows a memory array employing a memory cell having a single EPROM element. Several additional switching and load devices are required in the memory array to adequately read, program and erase data. In addition, the EPROM cells require ultraviolet light to discharge the floating gates of the EPROM. Generally, the time required for such an erase cycle is prohibitively long compared to the minimal erase time required for a conventional EEPROM.
A single transistor memory cell is most desirable in a programmable, non-volatile memory array. The transistor used in such a memory array is typically a floating gate field effect transistor that uses the Fowler-Nordheim tunneling mechanism during the erase cycle. One problem with use of the Fowler-Nordheim tunneling mechanism during the erase cycle is that the floating gate in the transistor can become over-erased. During the erase cycle negative charges on the floating gate are discharged from the floating gate. This discharging of negative charges cannot be precisely controlled, and can lead to an excess discharge of negative charges during the erase cycle. When an excess of negative charge has been removed, a net positive charge remains on the floating gate after the erase cycle. This positive charge causes an unwanted channel under the floating gate when the control gate is selected for a read cycle. Under certain circumstances, the channel allows a current flow from the drain to the source providing erroneous data.
One solution to the problem of over-erasing the floating gate is to add a second transistor to each cell to block output of erroneous data resulting from the over-erased floating gate. This two-transistor cell then forms each EEPROM memory cell.
Several drawbacks exist, however, in the use of EEPROM memory cells. One drawback is that EEPROM memory cells require sophisticated manufacturing processes, thus increasing their cost of manufacture. A second drawback is that EEPROM memory cells require two transistors per cell and, as such, require more surface area on a silicon wafer than a single transistor cell, thereby further increasing cost.
One approach of simplifying the EEPROM memory cell has been to use a split gate memory cell that is essentially the EEPROM memory cell combined into a hybrid two transistor design that requires less area on a silicon wafer. The manufacturing process for the split gate transistor is less sophisticated than that for the EEPROM memory cell, but is still more sophisticated than that for a single transistor memory cell. Furthermore, the split gate cell also requires more area than a single transistor cell.
Therefore, what is needed is a non-volatile memory array having a single transistor memory cell which array is not susceptible to read errors caused by having an over-erased floating gate.